3D Sequential Integration (3DSI) enables the vertical stacking of multiple device layers with a unique via density exceeding 108 vias/mm². The devices are sequentially stacked on the same substrate, raising concerns about the impact of the top device fabrication process on the performance of the bottom devices, for example. The presentation will address the technological challenges of 3DSI, such as the thermal stability of bottom devices, contamination issues during device stacking, top device channel creation, and the fabrication characteristics of top device MOSFETs. It will also showcase the current status and demonstrations of this technology for both More Moore and More than Moore applications.