Hands-on Session

Four practical sessions are organized in parallel during the conference :

• Hands-on session chair: Philippe T.
• Session 1: Security of System-On-Chip
• Session 2: RISC-V and System-On-Chip
• Session 3: Embedded AI on FPGA
• Session 4: Embedded AI in intelligent systems and devices

All sessions will be held on Thursday 12 June, from 2:00 pm to 4:00 pm.
You would either attend to the general assembly of the GDR or one hands-on session.

Session 1: Security of System-On-Chip

• Title: Damn Vulnerable IoT SoC
• Trainer: Philippe Tanguy and Adam Henault (Lab-STICC/ARCAD)
• Training level: Beginner
• Venue: To Be Confirmed
• Participants: To Be Confirmed
• More details: Damn Vuln IoT SoC is a modular platform to generate SoC with hardware vulnerabilities, based on an instrumented version of LiteX SoC generator. This tool can be used for educational purposes, CTF or HDL analysis tool. During the session, we will present the platform and then propose a game in which each team will have to hunt for Bugs in a vulnerable SoC and will be able to demonstrate their exploits on a real use case with an FPGA board.

Session 2: RISC-V and System-On-Chip

• Title: RISC-V and SoC
• Trainer: Florent De Lamotte (Lab-STICC/SHAKER)
• Venue: room S002 building ENSIBS
• Training level: Intermediate
• Participants: 16 maximum
• More details: The NEORV32 is a customizable microcontroller core from https://neorv32.org. It is built around the RISC-V architecture and comes as a VHDL implementation. We've been using it successfully for teaching on Cyclone-V based DE0-Nano boards and we propose to show you how this platform can be used for that purpose. After a brief introduction, we'll explore the configuration of NeoRV as a standalone processor using its internal peripherals and how to program it. We'll then explore expanding it with the Sopc-builder tool that comes with Quartus to access external peripherals such as the ADC and use external SDRAM. Experiments will be carried on a mobile robot platform.

Session 3: Embedded AI on FPGA

• Title: Developing AI Inference Solutions with the Vitis AI Platform
• Trainer: Dominique Heller (Lab-STICC/SHAKER)
• Venue: room 107 building UFR Science 1
• Training level: intermediate
• Participants: 12 maximum
• More details: This tutorial describes how to use the Vitis™ AI development platform to infer a yolov7 classification model on a Xilinx Ultra Scale + kv/kr260 board. During the session, we will present the Vitis AI platform and the flow : Post training quantization, Quantization Aware Training, Compilation, Inference with DPU PYNQ, Power Monitoring and Profiling.

Session 4: Embedded AI in intelligent systems and devices

• Title: Embedded AI with Aidge
• Trainer: C. Moineau (CEA List)
• Venue: To Be Confirmed
• Training level: Intermediate
• Participants: To Be Confirmed
• More details: Deep neural networks have emerged as the dominant solution for numerous applications. However, their increasing complexity necessitates substantial computational power, which presents considerable obstacles for deployment in embedded and real-time contexts. This tutorial provides an exploration of fundamental embedded AI concepts and introduces Aidge (https://gitlab.eclipse.org/eclipse/aidge), an open-source platform tailored for developing deep neural networks for resource-constrained environments. We will begin with a brief overview, followed by an exploration of Aidge's features across a standard application development pipeline: model creation or import, model transformations, training and optimization using techniques like quantization and compression, and finally, generating the corresponding source code to enable inference on hardware.