The RISC-V ecosystem is rapidly expanding and has gained significant traction within the FPGA community due to its allowance for free customization of both the Instruction Set Architecture (ISA) and microarchitectural features. However, designing the corresponding microarchitecture remains costly and error-prone. To address this challenge, we propose a High-Level Synthesis (HLS) flow capable of automatically synthesizing pipelined microarchitectures from a purely behavioral description of their instruction set. Our approach integrates insights from our prior work on speculative pipelining with a design space exploration phase to fully automate the inference of the processor's microarchitecture. Our results demonstrate that this flow is sufficiently general to support a variety of ISA and microarchitectural extensions and can produce circuits that are competitive with those manually designed.